1. Field of the Invention
The present invention relates to a memory device and, more particularly, to a programmable read-only memory.
2. Description of the Prior Art
RAMs (random access memories) and ROMs (read-only memories) are memory devices which are used in a variety of electronic machines such as electronic computers. ROMs include PROMs (programmable ROMs), one type of which is the bipolar PROM.
As is well known in the art, PROMs are divided into those using fuses and those using diodes. In the former type of PROM, data is written by applying a constant voltage of several volts to melt a fuse made of polysilicon or nichrome. In the latter type of PROM, on the other hand, the data writing operation is conducted bit by bit by destroying PN junctions with constant-current pulses of a pulse width of about 10 .mu.secs. As a result, after writing data therein PROMs cannot have their data erased.
Semiconductor memory devices are used widely, not only in microcomputers and minicomputers, but also in large-scale computers, as their capacities and speed continue to increase, and their power consumption increase. With the increase in capacity and speed, the components of the semiconductor memory devices are reduced further in size so that the fabrication process thereof becomes even more complex. Even a slight difference in the fabrication process conditions results in the completed memory devices having variations in their characteristics, which may cause the products to fail to meet their desired specifications. Accordingly, semiconductor memories must be checked for compliance with specifications before shipment to the user. For example, it is necessary to check whether or not the access time (i.e., the time interval from the instant when an input specifying an address is given, to the instant when the data stored in the predetermined memory cell is read out) meets the required specification. As has been described above, however, since no data can be written into the PROM before the user uses it, checking for compliance with the access time specification of a PROM has not been possible.
The present inventors have, therefore, developed a system by which specifications are checked, by providing and using a checking memory cell which is separate from the memory cell used by the user and which has data written into it in advance at the fabrication stage.
FIG. 1 is a schematic circuit diagram of a portion of a semiconductor memory device developed by the present inventors before the present invention. The checking method will be described with reference to FIG. 1. Memory cells C.sub.1, C.sub.2, C.sub.3, C.sub.4, C.sub.5, C.sub.6, C.sub.7, C.sub.8 and C.sub.9 are provided so as to intersect word lines Xl.sub.1, Xl.sub.2 and Xl.sub.3 and bit lines Yl.sub.1, Yl.sub.2 and Yl.sub.3. Memory cells C.sub.1, C.sub.2, C.sub.3, C.sub.6 and C.sub.9 are used for checking operations, and memory cells C.sub.4, C.sub.5, C.sub.7 and C.sub.8 provide memory circuits which are used as required by the user.
During checking, a voltage signal of about 8 V is supplied to a word input X and a bit input Y. The voltage level of 8 V is that used in the checking. Two values of 0 V and 3 V are used when the user is using the PROM. In FIG. 1, the threshold voltages of inverters IV.sub.1 and IV.sub.5 are set at 7 V, and those of inverters IV.sub.2, IV.sub.3, IV.sub.4, IV.sub.6, IV.sub.7 and IV.sub.8 at 1.5 V. The setting of the threshold voltages of the inverters associated with the checking memory cells at a higher value is designed to prevent the user from reading the data written into the checking memory cells during the manufacture of the PROM.
A method of selecting the directions of the word lines of the checking memory cells will now be described. The word lines and bit lines are selected when they go high. The word lines Xl.sub.2 and Xl.sub.3 are not selected. When the voltage signal of 8 V is supplied through the word input X and the bit input Y, the output of the inverter IV.sub.1 of checking circuit 1 goes to a low level (L level), and the output of the inverter IV.sub.2 goes to a high level (H level). As a result, the output of a word driver A.sub.1 goes high so that the word line Xl.sub.1 is selected.
Similarly, the output of the inverter IV.sub.5 forming a checking circuit 2 goes to L level, and the output of the inverter IV.sub.6 goes to H level. The output of the inverter IV.sub.7 also goes to L level, and the output of the inverter IV.sub.8 to H level. As a result, the input terminal a of an AND circuit A.sub.11 goes to L level. The input terminals a and b of an AND circuit A.sub.12 respectively go to H level and to L level. The outputs of the AND circuits A.sub.11 and A.sub.12 are fixed at L level irrespective whether the data written in the memory cells C.sub.1 and C.sub.2 is at the level "1" or "0". Since the input terminal a of an AND circuit A.sub.13 is at H level, the data stored in the memory cell C.sub.3 is outputted from the AND circuit A.sub.13, and through NOR circuit O.sub.1. Thus, the data in the memory cell C.sub.3 is read out.
In each memory cell, the state in which either the fuse is melted or the diode is destroyed corresponds to the level "1", and the undestroyed state thereof corresponds to the level "0".
When the memory cell C.sub.2 is to be checked, the voltage signal of 8 V is supplied to the word input X, and a voltage signal of about 3 V is supplied to the bit input Y. This selects the word line Xl.sub.1, as described above. Since the output of the inverter IV.sub.5 is at H level and the output of the inverter IV.sub.8 is also at H level, the bit line Yl.sub.2 is selected so that the data in the memory cell C.sub.2 is read out from the AND circuit A.sub.12.
When the memory cell C.sub.1 is being checked, moreover, the bit input Y is dropped to 0 V, so that the word line Xl.sub.1 is selected in the same way. However, the output of the inverter IV.sub.5 is at H level, and the inverter IV.sub.6 at L level. Moreover, the output of the inverter IV.sub.7 is at H level, and the output of the inverter IV.sub.8 is at L level. In this case, the bit line Yl.sub.1 is selected so that the data in the memory cell C.sub.1 is read out from the AND circuit A.sub.11. By changing the voltage levels of the word input X and the bit input Y in this manner, data is consecutively read out from the memory cells C.sub.1, C.sub.2, and C.sub.3 so that the characteristics of the memory can be checked by measuring the access time.
The description thus far concerns the data reading operation in the word line direction during the checking. The data reading operation in the bit line direction is conducted by fixing the bit input Y at the voltage level of 8 V, and by switching the voltage level of the word input X consecutively to 8 V, 3 V and 0 V. When the word input X is 8 V, the word line Xl.sub.1 and the bit line Yl.sub.3 are selected, as described above, so that the data in the memory cell C.sub.3 is read out. When the word input X is at 3 V, the word line Xl.sub.2 is selected so that the data in the memory cell C.sub.6 is read out. When the word input X is at 0 V, the word line Xl.sub.3 and the bit line Yl.sub.3 are selected so that the data in the memory cell C.sub.9 is read out. This means that the data in the checking memory cells C.sub.3, C.sub.6 and C.sub.9 can be consecutively read out in the bit line direction of the circuit and is used to measure the access time to perform the check. However, a variety of further investigations conducted by the present inventors on this semiconductor memory device have revealed the following problems.
When the user uses the PROM, the voltage levels of the word address input X and the bit address input Y are 0 V and 3 V, whereas a voltage level of 8 V is additionally used during the checking. As has been described above, when checking of access times is changed from the checking memory cells in the word line direction to that on the memory cells in the bit line direction, the voltage level of the word address input X must be switched from 8 V to 3 V to 0 V. Thus, the voltage levels for selecting a memory cell during checking is different from that used by the user and the resultant access time is different from that obtained during use which reduces the checking accuracy.
Since the threshold voltages of the inverters IV.sub.1 and IV.sub.5 in the first stages of the check circuits 1 and 2 are set at 7 V, and are different from the 1.5 V threshold value of the inverters IV.sub.3 and IV.sub.7 which are used by the user, the circuit configurations of the inverters is accordingly more complicated. As a result of the more complicated circuit configuration, the signal delay in the inverters is different so that the access time obtained by the checking is different from that during use which reduces the checking accuracy.
The problems thus far described have been discovered by the present inventors.